Verification of timed chi models using uppaal

Due to increasing system complexity and growing competition and costs, powerful techniques are needed to design and analyze manufacturing systems. One of the most popular techniques to do performance analysis is simulation. However, simulation-based analysis cannot guarantee the correctness of a system. Our research focuses on examining other methods to make performance analysis and functional analysis, and combining the two. One of the approaches is to translate a simulation model that is used for performance analysis to a model written in an input language of an existing verification tool. The process algebraic language χ is intended for modeling, simulation, verification and real-time control and has been used extensively to simulate large manufacturing systems. UPPAAL is an integrated tool environment for modeling, validation and verification of real-time systems and has been applied successfully in case studies ranging from communication protocols to multimedia applications. In this paper, we represent a translation scheme that is used to translate simulation models written in χ language to UPPAAL timed automata and show a small example of the translation. Future work includes defining an equivalence relation between χ and UPPAAL transition systems, implementing the translator as a part of the χ toolset, and applying it for verification of models of manufacturing systems.